Topic 12 of 20
GS Paper 3 Strategic Technologies Semiconductor self-reliance as defence strategy - niche chokepoint leadership versus full-stack replication

Designing the World's Chips, Owning None: Why DRDO Wants India to Hold a Chokepoint, Not the Whole Stack

Source PIB, Indian Express, Current Affairs AI, The NFA Post, Tradeint, Sanskriti IAS, Economic Times

One in every five chip designers on the planet works in India, yet the country imports about nine of every ten chips it uses. DRDO's own scientists have now said out loud what that gap means in wartime: a nation that draws the blueprints but cannot build, supply or own them has talent, not sovereignty.

Summary

At a curtain raiser on 13 October 2026 for the Semiconductors and Next-Gen Chips session of ESTIC-2026, senior DRDO scientists warned that India risks failing in future conflicts driven by AI, cyber and space power unless it becomes self-reliant in designing, making and deploying semiconductors by 2047.

They set out India's position: 20 per cent of the global chip-design workforce and 20 per cent of the data used for AI, but only 3 per cent of AI data centres and about 90 per cent import dependence. Because India cannot lead the entire semiconductor ecosystem, the scientists argued, it must lead chosen niches such as 2-nanometre chips, 3D structures, photonic integrated circuits and neuromorphic computing, aiming for at least two top-10 foundries and a 20 per cent share in top-niche technology by 2047.

WHY IT MATTERS FOR UPSC & STATE PCS

DRDO's leadership, including Director General B.K. Das, held a curtain raiser on 13 October 2026 for the semiconductor session of the Emerging Science, Technology and Innovation Conclave, due at Bharat Mandapam from 27 to 29 October 2026. Its scientists framed chip self-reliance as a condition for winning future wars, not only as an industrial goal.

Standard News

Talent Is Not Sovereignty: The Chip Stack India Draws but Does Not Own

Here's what's actually happening underneath the DRDO warning. A chip is not one product. It is a chain of four separate capabilities and a country controls a chip only if it controls enough of that chain that no one can switch it off.

  1. Design: the architecture, the software tools used to lay out billions of transistors and the licensed building blocks of intellectual property.
  2. Fabrication: the foundry, where a design is printed onto silicon wafers.
  3. Materials and equipment: wafers, specialty chemicals, gases and machines.
  4. Assembly and testing: packaging the finished die so it can be used. India's famous strength sits in the first layer, but only as labour. About 20% of the world's chip-design workforce, over 300,000 engineers, works in India. Much of that work has historically been done for global fabless firms, so the resulting IP belongs to them.

The Architect Analogy and Where It Breaks Think of

Indian chip engineers as skilled architects drawing towers for foreign developers. The drawings are excellent, but the land, the cement, the cranes and the title deed belong to someone else. The analogy breaks at one point and that point makes India's position worse.

An architect at least owns the pencil. A chip designer often depends on design-automation tools and IP licensed from abroad. DRDO's Dr Anesh Sharma reportedly placed US leadership in exactly this area: design automation, system architecture and IP.

So even the layer India is "good at" is not fully under its control. The other layers are thinner still:

  • Dr Sharma said India currently has no real expertise in fabrication, materials or semiconductor products.
  • Industry reports estimate that more than 90% of chip-making equipment and 85-90% of specialty chemicals and gases will still be imported.
  • India's chip import bill reached US$ 30.30 billion in FY25. In wartime, that is not a trade statistic. It is a list of switches someone else holds.

Why the Answer Is a Niche, Not a Replica

The sharp part of DRDO's argument is what it does not claim. Its scientists said India cannot lead the whole ecosystem by 2047. Instead it must lead some domains, because a country that owns something others need gains leverage: others listen. That is chokepoint logic turned around. Today, India is exposed to other countries' chokepoints. The 2047 goal is to hold a few of its own, such as:

  • 2-nanometre chips and 3D structures - photonic integrated circuits, which use light instead of electrons to move data - neuromorphic chips, which are built to imitate the brain's way of processing DRDO reportedly picked the last two because it has already started work there, hoping for early IP leadership. The proof that the approach can work already exists inside DRDO. In 2023, its Solid State Physics Laboratory developed indigenous gallium nitride MMICs, the high-power chips behind AESA radars. One material, mastered at home, closed one exposure.
For the exam, the insight is this: self-reliance in semiconductors does not mean making every chip. It means holding enough of the stack that India cannot be cut off and enough of a niche that others cannot cut India out.

Quick Facts

Key numbers & takeaways — revise these first

  • Event: DRDO curtain raiser for the Semiconductors and Next-Gen Chips session, 13 October 2026 Conclave: ESTIC-2026, Bharat Mandapam, New Delhi, 27 to 29 October 2026 India's share of the global chip-design workforce: about 20 per cent, over 300,000 engineers India's share of global data used for AI: 20 per cent; share of AI data centres: 3 per cent Import dependence for semiconductor needs: about 90 per cent Semiconductor import bill: US$ 30.30 billion in FY25, up from US$ 19.30 billion in FY23 2047 goals: leadership in 2nm chips and 3D structures, two foundries in the global top 10, at least 20 per cent share in top-niche technology India Semiconductor Mission outlay: Rs 76,000 crore, under MeitY Tata Electronics-PSMC fab at Dholera: 28, 50 and 55 nm nodes, silicon output expected mid-2028 SSPL, a DRDO lab, developed indigenous GaN MMICs in 2023 for AESA radars and electronic warfare

Beyond The Headlines
GS Paper 3 Semiconductor self-reliance as defence strategy - niche chokepoint leadership versus full-stack replication

Connect the dots for your UPSC preparation.

Standard news covers the event. Log in to read our comprehensive analysis and uncover the hidden constitutional, structural, and ethical dimensions of this topic:

1

Why India's world-class design workforce produces foreign IP and the structural causes behind the 90 per cent import gap in the upstream layers

2

A side-by-side check of the 2047 target of 2nm leadership against the 28 to 55 nm nodes India's first fab is actually building

3

The risks of a niche strategy: what happens if quantum, photonic and neuromorphic bets fail to produce IP before rivals lock in standards

4

A Short Term and Long Term way forward linking DRDO labs, the India Semiconductor Mission and the domestic design talent pool

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